1. Field of Invention
The present invention relates to a method for manufacturing semiconductor device. More particularly, the present invention relates to a method for manufacturing the lower electrode of a capacitor.
2. Description of Related Art
Dynamic random access memory (DRAM) is a device for storing digital data. Since DRAMs make use of a capacitor to store data, the capacitance of a DRAM capacitor should be sufficiently large so that data retention time can be longer. With the advent of ultra-large semiconductor integration (ULSI), the size of each memory cell in a DRAM is reduced. Consequently, the electrode surface area of a capacitor must somehow be increased in order to compensate for the drop in capacitance. For example, a hemispherical grained silicon (HSG) layer is deposited over an electrode plate of the capacitor to increase its surface area.
FIGS. 1A through 1F are cross-sectional views showing the progression of manufacturing steps in producing the lower electrode of a capacitor according to a conventional method. First, as shown in FIG. 1A, a semiconductor substrate 10 having field oxide layers 12 defining a device region is provided. Details of the devices within the device region are not shown in the figure. A dielectric layer 14 is formed over the substrate 10, and contact windows 16 are formed in the dielectric layer 14 exposing one of the source/drain region (not shown in the figure) of a transistor within the device region.
Next, as shown in FIG. 1B, a conductive layer 18 is deposited over the dielectric layer 14 and into the contact openings 16 making electrical connection with the source/drain region. The conductive layer 18 can be, for example, an ion-doped polysilicon layer deposited by a low-pressure vapor deposition process. Then, a cap dielectric layer 22 is deposited over the conductive layer 18 using, for example, a chemical vapor deposition method. The cap dielectric layer 22 can be made from, for example, borophosphosilicate glass (BPSG). Thereafter, photolithographic and etching processes are used to pattern the cap dielectric layer 22 and the conductive layer 18, finally forming the structure as shown in FIG. 1B.
Next, as shown in FIG. 1C, a layer of ion-doped polysilicon is deposited over the whole substrate structure using, for example, a low-pressure chemical vapor deposition (LPCVD) method. Thereafter, the polysilicon layer is etched back to form spacers over the sidewalls of the cap dielectric layer 22 and the conductive layer 18 using, for example, an anisotropic etching method.
Next, as shown in FIG. 1D, the cap dielectric layer 22 is removed to expose the conductive layer 18. The cap dielectric layer 22 is removed, for example, by a reactive ion etching (RIE) method employing gaseous hydrogen fluoride or hydrofluoric acid solution.
Next, as shown in FIG. 1E, a hemispherical grained silicon layer 26 is formed over the whole substrate structure including the conductive layer 18, the dielectric layer 14 and the spacers 24. The hemispherical grained silicon layer 26 can be deposited, for example, by a low pressure vapor deposition (LPCVD) method using a silane SiH.sub.4 or Si.sub.2 H.sub.6 as the source of reactive gas. The deposition of hemispherical grained silicon is preferably conducted at a temperature between the growth of amorphous silicon and the growth of polysilicon.
Next, as shown in FIG. 1F, the hemispherical grained silicon layer 26 above the dielectric layer 14 is removed using, for example, an anisotropic etching back operation. The conductive layer 18, the spacers 24 and the residual hemispherical grained silicon layer 26 together constitute the lower electrode of a capacitor. The reason for removing the portion of hemispherical grained polysilicon layer above the dielectric layer 14 is for preventing any electrical connection between two adjacent conductive layers 18. In other words, avoiding any damage to the semiconductor device caused by the electrical connection between any two lower electrodes of adjacent capacitors.
However, the whole hemispherical grained silicon layer 26 is exposed to the etchants when portions of the hemispherical layer 26 that lies over the dielectric layer 14 is removed in an etching back operation. Consequently, the remaining hemispherical grained silicon layer 26 will be damaged as well. Damage to that portion of the hemispherical grained silicon layer 26 that lies above the conductive layer 18 is especially serious, and may easily lead to leakage current from the subsequently deposited dielectric layer. Therefore, the etching operation must be carefully controlled in order to avoid too much damage to the hemispherical grained silicon layer 26.
Furthermore, if the back etching operation is not properly controlled, there may be residual electrical connection called micro-bridges linking up adjacent lower electrodes. These micro-bridges may cause short-circuiting path damaging both adjacent capacitors.
In light of the foregoing, there is a need for improving the method of forming the hemispherical grained silicon layer.